Experience

IBM | May 2026 - Aug 2026

SystemVerilog, C, C++, Python

NewHaptics | Aug 2025 - Mar 2026

Python, Docker

Led 4-person team to develop braille-accessible games for custom display hardware with 1,024 tactile dots
Leveraged custom HAL and Docker-based environment in PyCharm for hardware-independent testing
Set up GitHub with rulesets and Notion for task management, improving collaboration and version control
Reviewed all pull requests and enforced coding standards to ensure scalable, high-quality software delivery
Contributed software featured in company demos at CES and CSUN AT Conference 2026

University of Michigan | Sep 2023 - Apr 2024

Python, Embedded C, Raspberry Pi, I2C, MQTT

Prototyped 22/26 Midwest embedded IoT climate management system with potential 30% HVAC energy savings
Created Python script processing 17,000+ daily I2C sensor readings on RPi for real-time environmental monitoring
Researched and integrated sensors, relays, and specialized hardware for air exchange and window actuator systems
Implemented MQTT network protocols to enable less than 1-second latency in real-time sensor data transmission
Authored and presented research poster to 140+ attendees at annual MRADS Spring Research Symposium

Projects

Embedded C, STM32, DMA, SPI, UART (MIDI)

Architected 80MHz interrupt-driven STM32 firmware system for control of 5 concurrent hardware peripherals
Engineered 0.02° resolution feedback control using a 17.5k CPR encoder to align 4 strings for solenoid actuation
Implemented master/slave timer synchronization to coordinate cycle-accurate stepper motor bowing
Offloaded 20-LED and OLED data streams to DMA and SPI to maintain real-time motion control loop execution
Fabricated 15+ custom parts, including a specialized bridge and 3D-printed mounts, to integrate robotic actuators

Repo Link

SystemVerilog, RTL Design, Makefile, Synopsys VCS, Synopsys DC

Architected 2-way RISC pipeline with a micro-op queue to decouple instruction fetch from backend execution
Developed OoO execution engine with 3-issue window and hardware logic to resolve RAW/WAW/WAR hazards
Implemented split of register-offset loads/stores into discrete ADDI and memory micro-ops
Enabled non-blocking execution to allow independent ALU operations to bypass stalled memory load instructions
Integrated an instruction cache and 2-bank Branch Target Buffer (BTB) for predictive speculative execution